Tugas 3

1.   What general roles are performed by CPU registers?

Registermerupakan alat penyimpanan kecil yang mempunyai kecepatan akses cukup tinggi, yang digunakan untuk menyimpan data dan/atau instruksi yang sedang diproses

2.   What categories of data are commonly supported by user visible registers?

General purpose; Data; Address; Condition codes

3.   What is function of condition codes?

Kode kondisi adalah bit ditetapkan oleh hardware CPU sebagai hasil operasi. Misalnya, operasi aritmatika dapat menghasil kanhasil yang positif, negatif, nol, atau overflow. Selain hasil itu sen \diri disimpan dalam sebuah register ataumemori, kode kondisi juga di set. Kode selanjutnya dapat diuji sebagai bagian dari operasi cabang bersyarat.

4.   What is a program status word?

Program Status Word adalah register diprosesor yang meliputi control informasi untuk menentukan keadaan CPU.

5.   What are some typical distinguishing characteristics of RISC organization?

(1) a limited instruction set with a fixed format,

(2) a large number of registers or the use of a compiler that optimizes register usage, and

(3) an emphasis on optimizing the instruction pipeline.

6.      How are history bits used for branch prediction?

One or more bits that reflect the recent history of the instruction can be associated with each conditional branch instruction. These bits are referred to as a taken/not taken switch that directs the processor to make a particular decision the next time the instruction is encountered.

7.   List and briefly explain various ways in which an instruction pipeline can deal with conditional branch instructions.

8.      Multiple streams: A brute-force approach is to replicate the initial portions of thepipeline and allow the pipeline to fetch both instructions, making use of two streams.Prefetch branch target: When a conditional branch is recognized, the target of the branch is prefetched, in addition to the instruction following the branch. This target is then saved until the branch instruction is executed. If the branch is taken, the target has already been prefetched. Loop buffer: A loop buffer is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions, in sequence. If a branch is to be taken, the hardware first checks whether the branch target is within the buffer. If so, the next instruction is fetched from the buffer. Branch prediction: A prediction is made whether a conditional branch will be taken when executed, and subsequent instructions are fetched accordingly. Delayed branch: It is possible to improve pipeline performance by automatically rearranging instructions within a program, so that branch instructions occur later than actually desired.

9.   Briefly explain the two basic approaches used to minimize register-memory operations on RISC machines.

Two basic approaches are possible, one based on software and the other on hardware. The software approach is to rely on the compiler to maximize register usage. The compiler will attempt to allocate registers to those variables that will be used the most in a given time period. This approach requires the use of sophisticated program-analysis algorithms. The hardware approach is simply to use more registers so that more variables can be held in registers for longer periods of time.

10. If a circular register buffer is used to handle local variables for nested procedures, describe two approaches for handling global variables.

1) Variables declared as global in an HLL can be assigned memory locations by the compiler, and all machine instructions that reference these variables will use memory-reference operands.

(2) Incorporate a set of global registers in the processor. These registers would be fixed in number and available to all procedures

11.  What are some typical characteristics of a RISC instruction set architecture?

One instruction per cycle.Register-to-register operations.Simple addressing modes. Simple instruction formats.

12. What instruction level parallelism?

the term instuction - level parallelism refers to the degree to wich, on average, the instruction of a program can be executed in parallel.